1. Field of the Invention
The present invention relates generally to the field of semiconductor fabrication and, more particularly, to an alignment mark and alignment method for the fabrication of trench-capacitor dynamic random access memory (DRAM) devices.
2. Description of the Prior Art
Semiconductor integrated circuits undergo a variety of processing steps during manufacture, such as masking, resist coating, etching, and deposition. In many of these steps, material is overlaid or removed from the existing layer at specific locations in order to form the desired elements of the integrated circuit. Proper alignment of the various process layers is therefore critical. The shrinking dimensions of modern integrated circuits require increasingly stringent overlay alignment accuracy during pattern transfer. If the proper alignment tolerance is not achieved, the result is a device that is defective or has reliability problems.
Reduction type projection printing has been known as an apparatus of projection exposure for transferring a pattern drawn on a reticle to a resist. In reduction type projection printing process, a step and repeat method is used. The step and repeat method refers to a method of transferring a reticle pattern to a resist in which exposure is performed every time a wafer on a two-dimensionally movable x-y stage is moved in any given direction. A beam such as i-line or KrF laser is directed from a light source through a condenser lens to a reticle. The beam which passes through the reticle is projected on a photoresist on a wafer fixed on a wafer x-y stage through a reduction projection lens. Position of the wafer is automatically moved successively in x, y directions by the wafer x-y stage and the wafer is exposed shot-by-shot.
Registration is typically used to measure the accuracy of a process layer alignment performed using an alignment mark. Registration involves comparing the position of a subsequent layer to that of an existing layer by overlaying a distinct pattern on a matching pattern previously formed on the existing layer. The deviation in position of the overlay from the original provides a measure of accuracy of the alignment. Currently available registration structures include box-in-box visual verniers to determine the amount of alignment offset.
Trench-capacitor DRAM or deep-trench (DT) capacitor DRAM devices are known in the art. Typically, a trench-storage capacitor consists of a very-high-aspect-ratio contact-style hole pattern etched into the substrate, a thin storage-node dielectric insulator (capacitor dielectric), a doped low-pressure chemical vapor deposition (LPCVD) polysilicon fill, and buried-plate diffusion in the substrate. The doped LPCVD silicon fill and the buried plate serve as the electrodes of the capacitor. A dielectric isolation collar (collar oxide) disposed in the upper region of the trench prevents leakage of the signal charge from the storage-node diffusion to the buried-plate diffusion of the capacitor. After forming the trench capacitors, shallow trench isolation (STI) and active area (AA) regions are formed on the substrate between the trench capacitors. At the stage of forming the AA region, a very high accuracy of the AA-DT alignment is required.